Peculiarities of the architecture and structure of the reconfigure accelerator cards

Authors

  • Yurii Serhiiovych Yakovlev Institute of Cybernetics of the VM Glushkov National Academy of Sciences of Ukraine

Keywords:

reconfiguration, the accelerator, the "processor-in-memory", the programmed logical chip (PLC)

Abstract

Features of construction of accelerators with reconfiguration by usage are observed: diagrammes of connections for sampling of optimal resources of the accelerator; scalings of system at the expense of usage of the updated ring bus; applications the PLIS for an accelerator pattern under type of the solved task; architectures of type "processor-in-memory" with application of the offered method of allocation of the graphics task on system processors. Thus offered is architectural-structural solutions are protected by patents of Ukraine.

Author Biography

Yurii Serhiiovych Yakovlev, Institute of Cybernetics of the VM Glushkov National Academy of Sciences of Ukraine

Doctor. tehn. Sciences, Head. department

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How to Cite

[1]
Y. S. Yakovlev, “Peculiarities of the architecture and structure of the reconfigure accelerator cards”, ІТКІ, vol. 28, no. 3, Jun. 2014.

Issue

Vol. 28 No. 3 (2013): Information Technology and Computer Engineering

Section

Information technology and coding theory

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