ASSOCIATIVE PROCESSORS WITH PARALLEL-SERIAL DATA PROCESSING

Abstract

Development of associative memory and parallel methods of associative processing of numerical arrays allows to overcome the limitations of address (serial) access to memory and increase the speed of non-calculating operations. Among the methods of associative processing the most commonly used methods is processing method by bit cuts (slices), that is the simultaneous processing of the same names of bits of all words. In this paper the known variants of constructing associative processors, the base block of which is associative memory, is analyzed. An associative processor with a parallel-serial method of elements processing of a numerical array is selected. Two structures of associative processors with the ability to perform searches by key and search for a minimum / maximum in a numerical array are proposed. In the first proposed variant of the associative processor for the search by key in the numerical array, parallel-serial processing allows fixing the ratio of n operands with the key in the form of binary attributes (=, ≠) in the memory of the results on the triggers. In the second proposed version of the associative processor for search extreme numbers, the expansion of functionality is achieved by working in two modes: the search for a minimum or maximum number in an array of numbers. The feature of such processors is the using of fast register memory on counters and parallel processing without the operation of comparing elements of a numerical array. In this case, it`s possibly to combine the functionality of the two types of proposed associative processors in one associative processor due to the similarity of their structural organization and the principle of the elements processing of a numerical array using the operation of a decrement in the register memory on the counters. The basic parameters of the proposed associative processors are calculated. A comparative analysis of known and proposed associative processors is performed on indicators such as hardware complexity and time costs. A significant advantage of the proposed associative processor is the regularity of the structure and the smaller amount of hardware costs. The gain in hardware costs is important for   the implementing of associative processor on promising element base - FPGA.