IMPLEMENTATION OF MULTI-THREADING ON THE ARCHITECTURE OF NEXPERIA MULTIMEDIA PROCESSORS

Abstract

The structure of multiprocessor systems based on the architecture of modern Nexperia multimedia processors with a 32-bit computing core is considered. The fields of application of multimedia processors as general purpose processors and their data processing functions are studied. Multimedia processors use either functional architectures with limited flexibility but higher speed and efficiency, or programmable architectures with increased flexibility. The architecture of one of the Nexperia processors - TriMedia TM-1300 is analyzed and the diagram of its main components, the principle of operation of the central arbitration of the processor bus and methods of increasing its speed are given. Advanced general-purpose processors have been found to provide multimedia support by incorporating new multimedia instructions and executing them in parallel using a SIMD coprocessor approach. They provide multimedia support, including multimedia instructions in the instruction set. Instead of performing specific multimedia functions (such as compression and 3D graphics), multimedia processors provide purpose-built instructions to support general video processing operations. These instructions include support for 8-bit data types (pixels), efficient data addressing, and I/O instructions. The article examines the possibilities of software implementation of the parallelization of processors using parallel processing technologies, which is achieved by dividing one execution of a task into several independent smaller tasks. A software implementation of the work using a static and anonymous method is proposed. The program codes and the results of their testing are given. It has been proven that the division of different parts of the task between several computational resources of the CPU allows to reduce the execution time of the program and improves the potential computing power of the computer system.