NON-SEPARABLE BLOCK 9-BIT FAULT RESISTANT SINGLE ERROR CORRECTION CODES

Abstract

With the rapid development of digital telecommunication technologies, the usage of new methods to increase the speed and reliability of data transfer is becoming more relevant. Examples may include data encoding based on the artificial introduction of redundancy and enabling the receiving side not only to detect data distortions but also to form correct values. The separable codes (for example, the Hamming codes) are inferior to non-separable error correction codes in speed. But the increase in the speed of data transmission requires utilising complex, multipoaitional algorithms for searching maximal codes. This leads to an increase in the time of static proof codes determination compared to separable codes, although the speed of data transmission in operation is increased as well, having identical capacities for fault resistant.  Technology is proposed that is based on using 9-bit non-separable codes and the encoders/decoders for them, factoring in the fact of absence of the generalised theory of building them. Factoring in the aspects of specialised devices implementation based on an integral technology, the usage of FPGA technology is the most opportune.  For practical implementation of universal encodecs/decoders for 9-bit non-separable codes, an approach is proposed utilising FPGA that can be configured to any of these codes with any decimal numbers (the non-separable codes do not contain informational and test parts). Such properties of non-separable codes enable increasing the transmission speed of BCD words. Additionally, the obtained results could be a basis for the further development of a theory and practice for employing the block inseparable codes when the block size increases and it is a reassuring factor as for the analysis of non-separable codes in case of two or more errors correction.