ANALYSIS OF THE ARCHITECTURE OF SUCCESSIVE APPROXIMATION REGISTER ADC AND APPROACHES TO ITS IMPROVEMENT
DOI:
https://doi.org/10.31649/1999-9941-2023-57-2-4-12Keywords:
successive approximation register analog to digital convertor, capacitor digital-to-analog convertor, array of binary weighted capacitors, segment capacitor array, array with a split capacitorAbstract
Abstract. Successive approximation register analog-digital converters (SAR ADC) represent the majority of the ADC market for medium- to high-resolution ADCs. Modern SAR ADCs allow to ensure a sampling frequency of more than 100 MHz with a resolution of 10 to 12 bits. Features of the ADC architecture of this type: simplicity, high energy efficiency and dependency of conversion time from resolution. The two main components of a SAR ADC that affect its basic characteristics are the comparator and the digital-to-analog converter (DAC). The DAC based on a capacitor matrix is most often used. In practice, when implementing an ADC in an integrated view, when increasing the resolution, the natural increase of the chip area crystals, increase of the energy, which is consumed during the transformation, and decrease in productivity is intensified by number of technical and technological factors The work analyzes a number of modern approaches that are used to improve the characteristics of the SAR ADC in increased resolution. In particular, the segmentation of the DAC capacitor matrix or the division of the capacitor matrix into a matrix of binary weighted capacitors and a matrix of C-2C capacitors allows to reduce the range of required values of capacitor capacities and reduce the total capacity of the matrix. Due to this, in comparison with the basic architecture, when the ADC bit rate is increased, a smaller area on the crystal is required for the implementation of the matrix and higher performance is ensured. Replacing the capacitor of the most significant discharge of the matrix with an exact copy of its other part allows to reduce the energy consumed from the reference voltage source and spent on redistributing the charge between the capacitors of the matrix during conversion.
References
Y. Shen et al. A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique // IEEE Journal of Solid-State Circuits, 2020, vol. 55, № 3, pp. 680-692.
D. Li et al. A 1.4-mW 10-Bit 150-MS/s SARADC With Nonbinary Split Capacitive DAC in 65-nm CMOS // IEEE Transactions on Circuits and Systems II: Express Briefs, 2018, vol. 65, № 11, pp.1524-1528.
D. Luu et al. A 12-bit 300-MS/s SAR ADC with inverter-based preamplifier and common-moderegulation DAC in 14-nm CMOS FinFET // IEEE Journal Solid-State Circuits, 2018, vol. 53, №11, pp. 3268–3279.
Understanding SAR ADCs: Their Architecture and Comparison with Other ADCs. [Електронний ресур]. – Режим доступу: https://www.analog.com/en/technical-articles/successive-approximation-registers-sar-and-flash-adcs.html.
Jayamala Adsul, Harsh Sawardekar Reconfigurable Successive Approximation Register ADC and SAR-Assisted Pipeline ADC // A Journal of Physical Sciences, Engineering and Technology, 2021, vol. 13, № 2, рр. 93-97.
Y. Bocharov1 et al., Impact of switches resistance on successive approximation of ADC dynamic performance // IOP Conference Series: Materials Science and Engineering, April 2019; doi:10.1088/1757-899X/498/1/012005.
Huailiang Li1 , Jing Hu The Research on SAR ADC Integrated Circuit // Journal of Physics: Conference Series, Volume 1314, 3rd International Conference on Electrical, Mechanical and Computer Engineering 9–11 August 2019, Guizhou, China; doi:10.1088/1742-6596/1314/1/012022.
W. Guo, S. Liu, Z. Zhu An asynchronous 12-bit 50MS/s rail-to-rail Pipeline-SAR ADC // Microe-lectronics Journal, 2016, vol. 52, pp. 23–30.
W. Bontems, D. Dzahini Methodology for a Low-Power and Low-Circuit-Area 15-Bit SAR ADC Using Split-Capacitor Mismatch Compensation and a Dynamic Element Matching Algorithm // Chips, 2023, №2, рр. 31–43.
Lu Chi‐Chang , Huang Ding‐Ke 1.2 V 10-bits 40 MS/s CMOS SAR ADC for low-power applica-tions. // IET Circuits, Devices and Systems, 2019, vol. 13, №6, рр. 857–862.
Y. Zheng, F. Ye, J. Ren A 12-Bit, 100 MS/s SAR ADC Based on a Bridge Capacitor Array with Redundancy and Non-Linearity Calibration in 28 nm CMOS // Electronics 2022, 11, 705; https://doi.org/10.3390/electronics11050705.
Y. Zheng, J. Lan, F. Ye and J. Ren. A 12-bit 100MS/s SAR ADC with equivalent split-capacitor and LSB-averaging in 14-nm CMOS FinFET // IEEE Access, 2021, vol. 9, pp. 169107-169121.
C. Shetty, M. Nagabushanam, V. Prasad A 14-bit high speed 125MS/s low power SAR ADC using dual split capacitor DAC architecture in 90nm CMOS technology // International Journal of Circuits, Systems and Signal Processing, 2021, vol. 15, № 62, pp. 556–568.
Wu Y. et al. A design method of capacitor arrays for high-resolution SAR ADCs // Circuit World, 2020, vol. 46, № 4, pp. 249–255.
Cen Yuanjun et al. Design of Capacitor Array in 16-Bit Ultra High Precision SAR ADC for the Wearable Electronics Application // IEEE Access, 2020, vol. 8., pp. 175230-175243.
Ginsburg B., Chandrakasan A. An energy-efficient charge recycling approach for a sar converter with capacitive dac // Proceedings of the 2005 IEEE International Symposium on Circuits and Systems (ISCAS), May 2005; doi: 10.1109/ISCAS.2005.1464555.
Liangbo X. et al. Energy-efficient capacitor-splitting DACscheme with high accuracy for SAR ADCs // Electronics Letters, 2015, vol. 51, №. 6, pp. 460–462.
Tan S. et al. A 10-bit Split-Capacitor SAR ADC with DAC Imbalance Estimation and Calibration // Proceedings of the 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 12–14 October Seville, Spain, 2020; doi: 10.1109/iscas45731.2020.9180539.
Yunfeng H. et al. A 10 bit 1 MS/s SAR ADC with one LSB common-mode shift energy-efficient switching scheme for image sensor // Frontiers in Physics, 2022, vol. 10, pp. 82–95.
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