HIGH LINEARITY BALANCED PUSH-PULL DC AMPLIFIER WITH LOW ERROR OF ZERO OFFSET

Abstract

It is known that push-pull DC amplifiers (PPDA), as a rule, have a high linearity of the transfer characteristic, a wide passband (hundreds of MHz and GHz units) at the level of unity gain, and a significant rate of change in the output voltage (at least thousands of volts per microsecond). Serial models of such integrated PPDA are produced by Analog Devices, Texas Instruments, Linear Technology, National Semiconductor and others. Due to the presence of these characteristics, PPDA are widely used in current-voltage, current-current, ADC, DAC, direct digital synthesis systems and multi-channel digital systems for processing and recording analog signals.

Despite the high indicated static and dynamic characteristics of the PPDAs built on bipolar transistors, which have a significant additive error in the form of an input zero bias current of hundreds of nA and μA units. Often this can degrade the static parameters of these devices and systems. When the input zero bias current appears, there are basic currents of bipolar transistors in the input stages of the amplifiers. To reduce their influence in single-cycle current amplifiers, some special circuit methods are used. Which allow an order of magnitude to reduce the input zero bias current of the differential stage without affecting the bias voltage or speed.

To reduce the input zero bias current in the PPDA, it was proposed to apply basic current compensation in the input stages, as well as to build the input stages on Shiklai composite transistors, which will significantly improve the accuracy of the circuit as a whole.