HIGH-LINKED BUFFER AND VOLTAGE SCALE FOR BIPOLAR TRANSISTORS WITH LOW INPUT CURRENT
DOI:
https://doi.org/10.31649/1999-9941-2019-44-1-17-26Keywords:
voltage buffer, voltage scaler, push-pull DC amplifier, frequency responseAbstract
Buffer devices and voltage scalers are widely used in various analog-digital systems, when it is necessary to match the signal in the form of voltage from a low-power sensor to a load, it consumes significantly more power. In this case, the voltage buffer is characterized by a voltage transfer coefficient close to unity, and must also have a high input resistance and sufficient load capacity. The voltage scaler, in contrast to voltage buffers, must additionally provide the necessary gain transfer ratio, which can be substantially more than one. The circuit design features of three variants of the construction of voltage buffer cores and voltage scaling are considered. It is proved that it is advisable to reduce the input zero bias current by using amplifying n-p-n and p-n-p transistors, as well as Shiclay transistors in the input stages. The static and dynamic characteristics of the voltage buffers and the voltage scaler must meet the system requirements of the device. The static characteristics should be attributed primarily to the error of the transfer characteristics of the scale, zero offset and linearity. The dynamics of these devices is determined by the frequency response and transient response. Static and dynamic characteristics are analyzed by computer simulation where it is shown that the scale errors of the voltage buffers and the voltage scaler do not exceed 10 µV in the range of the corresponding signal ± 5 V, and the linearity errors are 300 nV. A transient response was obtained which states that the slew rate of the output voltage will be no worse than 2000 V/µs. A comparison of the metrological characteristics of the voltage buffers and the voltage scaler in the form of a set of cores and output push-pull DC amplifiers. It is proved that the use of these amplifiers allows significantly (by 3-4 orders of magnitude) to improve the load capacity of the circuits while maintaining the level of the input zero bias current, as well as scale and linearity errors.
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